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Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
FEATURES
* Very low threshold voltage * Fast switching * Logic level compatible * Surface mount package
PHK04P02T
SYMBOL
s
QUICK REFERENCE DATA
VDS = -16 V ID = -4.66 A RDS(ON) 0.15 (VGS = -2.5 V) VGS(TO) 0.4 V
d
g
GENERAL DESCRIPTION
P-channel, enhancement mode, logic level, field-effect power transistor. This device has low threshold voltage and extremely fast switching making it ideal for battery powered applications and high speed digital interfacing. The PHK04P02T is supplied in the SOT96-1 (SO8) surface mounting package.
PINNING
PIN 1,2,3 4 DESCRIPTION source gate
SOT96-1
8 7 6 5
5,6,7,8 drain
pin 1 index 1 2 3 4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tsp = 25 C Tsp = 100 C Tsp = 25 C Tsp = 25 C Tsp = 100 C MIN. - 55 MAX. -16 -16 8 -4.66 -1.87 -26.4 5.0 2.0 150 UNIT V V V A A A W W C
THERMAL RESISTANCES
SYMBOL Rth j-sp PARAMETER Thermal resistance junction to solder point CONDITIONS mounted on metal clad substrate. TYP. 25 MAX. UNIT K/W
May 2002
1
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = -10 A VDS = VGS; ID = -1 mA Tj = 150C VGS = -4.5 V; ID = -1 A VGS = -2.5 V; ID = -1 A VGS = -1.8 V; ID = -0.5 A VGS = -2.5 V; ID = -1 A; Tj = 150C Forward transconductance VDS = -12.8 V; ID = -1 A Gate source leakage current VGS = 8 V; VDS = 0 V Zero gate voltage drain VDS = -12.8 V; VGS = 0 V; current Tj = 150C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Input capacitance Output capacitance Feedback capacitance ID = -1 A; VDD = -10 V; VGS = -4.5 V MIN. -16 -0.4 -0.1 1.5 -
PHK04P02T
TYP. MAX. UNIT -0.6 80 117 140 175 4.5 10 -50 -13 7.2 1.7 1.83 2 4.5 45 20 528 200 57 120 150 180 230 100 -100 -100 V V V m m m m S nA nA A nC nC nC ns ns ns ns pF pF pF
gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ciss Coss Crss
VDD = -10 V; ID = -1 A; VGS = -8 V; RG = 6 Resistive load VGS = 0 V; VDS = -12.8 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tsp = 25 C, t 5 s IF = -0.62 A; VGS = 0 V IF = -0.5 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = -12.8 V MIN. TYP. -0.62 75 69 MAX. -4.66 -26 -1.3 UNIT A A V ns nC
May 2002
2
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
PHK04P02T
Normalised Power Derating, Ptot (%)
Zth j-sp (K/W) 100 10 1 0.1 single pulse D = 0.5 D = 0.2 D = 0.1 D = 0.05 D = 0.02 P D tp D = tp/T
100 90 80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160
Ambient temperature, Ta (C)
0.01 0.001 1E-06
1E-02
1E-05 1E-04 1E-03 1E-02
T
1E-01
1E-01 1E+00 1E+01 Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta)
Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T;;
Drain current, ID (A) -5
Normalised Current Derating, ID (%)
120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 160
Ambient temperature, Ta (C)
-4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0
-4.5 V
-1.8 V -2.5 V
Tj = 25 C
-1.3 V -1.2 V -1.1 V -1 V -0.9 V VGS = -0.8 V
-0.5 -1 -1.5 Drain-Source Voltage, VDS (V)
-2
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); conditions: VGS -10 V
Peak Pulsed Drain Current, IDM (A) tp = 1ms 10 ms 100 ms 1
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms) 0.7 0.6
100
-0.8 V -0.9 V
-1V
-1.1 V -1.2 V -1.3 V
Tj = 25 C
10
RDS(on) = VDS/ ID
0.5 0.4 0.3 0.2 -2.5 V -1.8 V
0.1
DC
0.1 VGS = -4.5V 0
0.01 0.1 1 10 100 Drain-Source Voltage, VDS (V)
0
-0.5
-1
-1.5 -2 -2.5 -3 Drain Current, ID (A)
-3.5
-4
-4.5
-5
Fig.3. Safe operating area. Tsp = 25 C; ID & IDM = f(VDS); IDM single pulse; parameter tp.
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
May 2002
3
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
PHK04P02T
Drain Current, ID (A) -5 VDS > ID X RDS(on) -4 -3 -2 -1 0 0 -0.5 -1 -1.5 Gate-Source Voltage, VGS (V) -2 Tj = 25 C 150 C
0.7 0.6 0.5 0.4 minimum 0.3 0.2 0.1 0 0 25 50 75 100 125 150 Junction Temperature, Tj (C) typical
Threshold Voltage, VGS(to), (V)
Fig.7. Typical transfer characteristics; ID = f(VGS)
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Drain Current, ID (A) 1E-01 VDS = -5 V Tj = 25 C
Transconductance, gfs (S) 8 7 6 5 4 3 2 1 0 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 Drain Current, ID (A) VDS > ID X RDS(on) Tj = 25 C 150 C
1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 -1
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 Gate-Source Voltage, VGS (V)
0
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C
Capacitances, Ciss, Coss, Crss (pF) 1000 Ciss Coss
1.6 1.4 1.2 1.0 0.8 0.6
Normalised Drain-Source On Resistance
RDS(on) @ Tj RDS(on) @ 25 oC VGS = -4.5 V -1.8 V -2.5 V
100 Crss
0
25
50
75
100
125
150
10 -0.1
Junction Temperature, Tj (C)
-1.0 -10.0 Drain-Source Voltage, VDS (V)
-100.0
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
May 2002
4
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
PHK04P02T
Gate-source voltage, VGS (V) -5 -4 -3 -2
1 5
Source-Drain Diode Current, IF (A)
VDD = 10 V s RD = 10 Ohms Tj = 25 C
4 3 2 150 C Tj = 25 C
-1
0
0 0 1 2 3 4 5 6 Gate charge, (nC) 7 8 9
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
May 2002
5
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PHK04P02T
D
E
A X
c y HE vMA
Z 8 5
Q A2 pin 1 index Lp 1 e bp 4 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024
0.028 0.004 0.012
8 0o
o
ISSUE DATE 95-02-04 97-05-22
Fig.15. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8".
May 2002
6
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode MOS transistor
PHK04P02T
DEFINITIONS
DATA SHEET STATUS DATA SHEET STATUS1 Objective data PRODUCT STATUS2 Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A
Preliminary data
Qualification
Product data
Production
Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. May 2002 7 Rev 1.000

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